A circuit technology which amplifies a difference in potential between a bit line pair using a preamplifier having a configuration in which a bit line is coupled to the gate and drain of each MOS transistor with respect to each memory cell that performs a low current operation upon reading and which assists in a differential amp operation of a subsequent stage, has been disclosed in a patent document 1. For example, one data line is coupled to one differential input terminal of a differential amplifier and one data line is coupled to the other differential input terminal of the differential amplifier. The one data line can be discharged by a parallel circuit of n channel type first and second MOS transistors, whereas the other data line can be discharged by a parallel circuit of n channel type second and second MOS transistors. The gate of the first MOS transistor is coupled to the one data line and the second MOS transistor is coupled to the other data line. The gate of the third MOS transistor is coupled to the other data line and the fourth MOS transistor is coupled to the one data line. When both data lines are precharged before the read operation and thereafter memory cells coupled to one data line are selected, a current corresponding to the difference in conductance between the selected memory cells flows through the one data line. An intermediate reference current based on the difference in conductance flows through the other data line. Thus, a difference in potential is formed between both data lines. At this time, the first through fourth MOS transistors are coupled to a circuit's ground to form discharge paths for the data lines. Since the current that flows through the first and second MOS transistors and the current that flows through the third and fourth MOS transistors become equal to each other by coupling configurations of the first through fourth MOS transistors, the difference in potential between both data lines is amplified by the time accumulation of differences in current value. This thus enables high-speed reading even when a read signal level is small.
Patent Document 1: Japanese Unexamined Patent